1. Field of the Invention
The present invention relates to a semiconductor memory device, more particularly, to a nonvolatile ferroelectric memory device having a split word line (SWL) structure.
2. Discussion of the Related Art
A ferroelectric memory, i.e. ferroelectric random access memory (FRAM), having data processing speed as fast as DRAM which is generally used as semiconductor memories and keeping the stored data when a supplied power is off is getting attention in the memory of next generation.
The FRAM is a memory device having almost the same structure as the DRAM but the data stored in the FRAM is not cleared even when electric field is lost from the memory by using ferroelectric material having a characteristic of a high residual polarization. In other words, as shown in the hysteresis loop of FIG. 1, a polarization induced by an electric field is not vanished because of the existence of its spontaneous polarization even though the electric field is removed but maintains a constant state (d and a states). This device is used as a memory by corresponding d and a states to 1 and 0, respectively.
Referring to figures, the conventional ferroelectric memory is explained as follows.
FIG. 2 is cell array structure of a conventional ferroelectric memory. The unit cell structure of the conventional FRAM consists of one transistor and one capacitor (1T/1C) which is similar to an existing DRAM. That is, a plurality of word lines (W/L) separated by equal distance are formed in one direction. A plurality of plate lines (P/L) are formed between the word lines in parallel to the each W/L. A plurality of bit lines (B.sub.-- n, B.sub.-- n+1, B.sub.-- n+2, . . . ) separated by equal distance are formed in the perpendicular direction to each of the word lines and the plate lines. The gate electrode of one transistor forming a unit memory cell is connected to the word line (W/L) and the source electrode of said transistor is connected to its neighboring bit line (B/L). The drain electrode of the transistor is connected with a first electrode of a capacitor and the second electrode of the capacitor is connected to its neighboring plate line (P/L).
The driving circuit and its operation of the ferroelectric memory device having the conventional 1T/1C structure like this are explained as follows.
FIGS. 3a and 3b show the diagram for the driving circuit of the conventional ferroelectric memory. Since the driving circuit of the ferroelectric memory having the conventional 1Y/1C structure includes a reference voltage generator 1 generating a reference voltage, a plurality of transistors Q1.about.Q4, and a capacitor C1, the output voltage signal generated from said reference voltage generator 1 can not be directly applied to the sense amplifier. Therefore, the driving circuit is constructed so as to include a reference voltage stabilization circuit 2 to stabilize the reference voltage of the adjacent two bit lines, a first reference voltage storage circuit 3 which consists of a plurality of transistors Q6.about.Q7 and capacitors C2.about.C3 and stores the reference voltages of logic value 1 and logic value 0 at its adjacent bit lines, respectively, a first equalizer 4 which consists of transistor Q5 and equalizes the adjacent two bit lines, a first main cell array 5 which is connected to word lines and plate lines different from each others and stores data, a first sense amplifier 6 which consists of a plurality of transistors Q10.about.Q14 and P-sense amplifier (PSA) and detects the data of the cell selected in the first main cell array 5 by said word line, a second main cell array 7 which is connected to word lines plate lines different from each others and stores data, a second reference voltage storage circuit 8 which consists of a plurality of transistors Q27.about.Q28 and capacitors C9.about.C10 and stores the reference voltages of logic value 1 and logic value 0 at its adjacent bit lines, respectively, and a second sense amplifier 9 which consists of a plurality of transistors Q15.about.Q24 and N-sense amplifier (NSA) and detects the data of the cell selected in said second main cell array 7 by said word line.
The input and output operations of the ferroelectric memory cell having the conventional 1T/1C structure are as follows.
FIG. 4 is a timing chart showing the operation of write mode of the conventional ferroelectric memory and FIG. 5 is a timing chart showing the operation of read mode of the conventional ferroelectric memory.
In write mode, the write mode begins when the chip selection signal CSBpad is enabled by the transition from a high state to a low state and at the same time the enable signal WEBpad is changed from a high state to a low state.
When an address decode operation begins in the write mode, a pulse being applied to the corresponding word line (W/L) is changed from a high state to a low state and a cell is selected. Thus, in the interval that the word line holds a high state, a high signal having a definite interval and a low signal having a definite interval are in order applied to the corresponding plate line (P/L) and a high or low signal synchronized with said write enable signal is applied to the corresponding bit line so as to write a logic value high or low into the selected cell.
In other words, in the interval that a high signal is applied to a bit line and a high pulse is applied to a word line, a logic value 1 is written into the corresponding ferroelectric capacitor if a low pulse is applied to the plate line.
When a low pulse is applied to a bit line and a high pulse is applied to a word line, a logic value 0 is written into the corresponding ferroelectric capacitor.
The operation of reading the data written in the cell according to the write mode is as follows.
When the chip select signal CSBpad is enabled by changing from a high state to a low state, all bit lines are set to an equal potential by an equalization signal before the corresponding word line is selected. For example, when a high pulse applied to the equalizer 4 in FIG. 3a and a high signal is applied to the transistors (Q18.about.Q19), the bit lines are grounded through the transistors (Q18.about.Q19) and are set to the equal potential.
After each bit line is made inactive by turning off the transistors (Q5, Q18, Q19) off and the address is decoded, the signal of the corresponding word line is changed from a low state to a high state by the decoded address so that the corresponding cell is selected.
By applying a high signal to the plate line of the selected cell, the data corresponding to a logic value 1 in the ferroelectric memory is destroyed. However, if a data corresponding to a logic value of 0 is stored in the cell, the data is not destroyed.
Thus, a destroyed data and an undestroyed data are present as the output signals different from each other according to the hysteresis curve as described above and are sensed as a logic value 1 or 0 by the sense amplifier.
The case that the data is destroyed is corresponding to the transition from point d to the point f on the hysteresis of FIG. 1 and the case that the data is undestroyed is corresponding to the transition from point a to the point f. Therefore, the output of the sense amplifier is a logic value 1 when the sense amplifier is enabled by an enable pulse and the data is destroyed. On the contrary, the output of the sense amplifier is a logic value 0 when the sense amplifier is enabled by an enable pulse but the data is not destroyed.
To restore the original state in the memory after the sense amplifier senses the data, amplifies the sensed signal and generates an output signal, the plate line is made inactive under the condition that a high pulse is applied to the corresponding word line.
In the conventional ferroelectric memory having the 1T/1C structure, since a reference cell performs much more data input and output operations than a main memory cell, the reference cell tends to be rapidly deteriorated.
The conventional ferroelectric memories and their driving circuits have problems as follows.
First problem is that the conventional FRAM has a complex layout because of their separated plate lines in spite of their merit holding the data even when the power is off.
Second problem is that the speed of the conventional FRAM decreases because the data input and output operations are done by the separated plate lines and a control signal is applied to the plate lines for the data read and write operations.
Third problem is that a reference voltage is not stabilized because one reference cell processes all the read operations of several hundred main memories and therefore the degradation is rapidly progressed.
Fourth problem is that a method for generating a reference voltage by a voltage control circuit is not stable because the reference voltage is affected by an external supply voltage variation and the characteristic change of the memory is caused by an external noise.
Fifth problem is that a high speed access is not achieved because only the chip select signal CSBpad is used for activating the ferroelectric memory.